RSS Feeds
Power Management Relies on Packaging
Improvements seal the deal for performance
Randy Frank, Contributing Editor -- Design News, November 3, 2008
The power that can be managed by power management circuitry is directly related to its packaging characteristics. Processing and semiconductor technique improvements turn out to be necessary but not sufficient without the right package. The alternative to optimum device-level packaging is higher internal temperature in the end product, the need for increased thermal considerations such as fans or larger heatsinks or plan B — a larger package or more packages. With applications from personal computers to portable consumer products to automobiles driving packaging innovation, power management companies have tackled packaging issues head-on with highly innovative approaches.
Unique Package Design
The semiconductor industry typically relies on open industry standard packages registered by the JEDEC Solid State Technology Assn. to drive high-volume production in the industry and ease-of-use in PC board assembly. International Rectifier’s (IR’s) DirectFET design is one package that bucks this trend. Although it was introduced more than six years ago for computer power supplies, DirectFET packaging continues to be a unique design to solve heat transfer in an industry-standard footprint supported by competition-restricting patents. Compared to traditional designs, the package uses direct chip attachment with no wire bonds or lead-frame and has top-side cooling. Expanded to two different sizes, the packaging methodology competes with industry-standard SO-8, DPAK, TSSOP-8 and Micro8 packages.
“Packaging represents about 50 percent of the power conversion stage performance and value proposition,” says Tim Phillips, vice-president, Enterprise Power Business Unit, International Rectifier. “The power conversion stages often run at their thermal limit, which is defined as much by how easily the heat is removed from a semiconductor as how much heat is generated by its performance in the first place.”
The DirectFET package addresses these concerns with lower package impedance and lower parasitic inductance resulting in reduced heat generation. At the same time, the double-sided cooling greatly enhances the removal of heat from the semiconductor. The lower package inductance also allows operation at higher frequencies for additional system-level efficiency improvement.
The initial DirectFET design had a thermal resistance from junction to PC board of less than 1 C/W in the same footprint as an SO-8 with more than 90 percent lower die-free package resistance and a 0.7 mm profile compared to 1.75 mm.
IR recently introduced a DirectFET chipset for a 25V synchronous buck converter consisting of the IRF6710S2 control MOSFET and IRF6795M and IRF6797M synchronous MOSFETs with integrated Schottky diodes. The combination of improved silicon and packaging designs provide increased efficiency and thermal performance and enable operation in excess of 25A per phase.
One measure of the package’s success is the licensing of the patented technology to competitors. IR licensed the DirectFET technology to two semiconductor companies in 2007. Known as the PolarPAK at Vishay Intertechnology, Vishay introduced several products that also target telecom and data communications applications providing a second source, in some cases, to IR products.
Smallest Footprint
Cramming more features into portable products puts space at a premium, increases thermal problems and decreases battery life. With its MICRO FOOT chip-scale package, Vishay provides the industry’s smallest footprint, 1.2 x 1.0 mm, for a 20V P-channel power MOSFET. The Si8445DB is 20 percent smaller than the industry’s next-smallest device with the same 0.59-mm profile and achieves an on-resistance (Rds(ON)) of 0.495Ω at a Vgs of 1.2V. In either case, achieving this level of on-resistance previously required paralleling two or more packages.
The chip-scale package uses die bump technology instead of wirebonds to connect directly to a PC board. Its maximum junction-to-ambient thermal resistance is 70 C/W and its maximum steady state junction-to-foot (drain) rating is 1 C/W. While variations of the so-called packageless technology have existed at several companies for many years, shrinking the size or taking advantage of the packaging capability with newly designed silicon extends its use into new applications. Vishay expects to see this package used in battery management in portable devices such as cell phones, PDAs, digital cameras, MP3 players and smart phones.
Reducing Packaging Resistance
Very high current power management applications can require breaking with tradition. That is exactly what STMicroelectronics did to achieve a 250A rated MOSFET with a typical on resistance of 1.5 mΩ (less than 2.2 mΩ max) in a Power SO-10 package. The STV250N55F3 has a junction-to-case thermal resistance of 0.5 C/W and a junction-to-PC board thermal resistance of 50 C/W when mounted on a 1 inch2 FR-4 with 2-oz copper traces. Introduced late last year, the lower voltage STV300NH02L can handle 280A and has a typical on-resistance of 0.8 mΩ with a maximum of 1mΩ.
STMicroelectronics pioneered the power SO-10 package more than 10 years ago and it was originally targeted for automotive applications. Recently, the company changed from traditional wirebonds to a ribbon bonding technique. However, the ribbon bonding technique is not new either. “Ribbons have been around and ST pioneered them more than 15 years ago,” says Vipin Bothra, applications manager, Power Applications, STMicroelectronics. In the Power SO-10, three continuous pieces of ribbon replace as many as 12 wirebonds. “The numbers vary depending on what particular device we are talking about and what current level we are talking about,” says Bothra.
The 280A MOSFET targets the OR-ing function where two 48V power supplies are tied together. For this application, the need for low Rds(ON) is tremendous because any lost power reduces the output power and directly impacts efficiency. Other OR-ing applications such as 12V power supplies could benefit from the technique, so there is a good chance ST will have a product that targets this voltage. “This particular part is targeted for several power supply applications,” says Bothra.
Since packaging can account for as much as 50 percent of the on-resistance in the high current, low voltage range, there is a definite value to reducing its contribution to the total, especially for applications such as OR-ing.“The limiting factor in the design is strictly the on-resistance and how much power you can dissipate in a given physical environment that you have,” says Bothra. “So, in the majority of the cases, it is the on-resistance that defines how much current you can have in actual applications.” Nine of the 10 pins in the Power SO-10 are used to handle the source current.
Using the ribbons instead of wires does not require a change in assembly process or materials or in the silicon wafer fabrication. In fact, the only difference in silicon design is the bond pad layout that needs to be revised for the ribbon bonding. An added benefit of the ribbon bonding is lower mechanical stress during the bonding process. Since it is used for automotive applications, the package has a maximum operating junction temperature of -55 to 175C. At this point, the STV250N55F3 does not have an automotive qualification even though it is in the right voltage range. ST expects an automotive qualification to be completed in the near future.
Package-Level Integration
Integration is the semiconductor industry’s trick to get more into the same space. With power, the same techniques that work so well for integrated circuits do not necessarily apply because of thermal constraints. Packaging can provide the answer for reducing the chip count and cutting the board space. This is the approach Renesas Technology used in its RJK0383DPA for higher-efficiency synchronous-rectification DC/DC converters.
Improved silicon design mounted in a WPAK3 package provides the same level of power supply efficiency yet reduces the chip mounting area to about half that of a dual-package power MOSFET design. While performance advantages result primarily from improved silicon, the ability to isolate two die and have each with a straight thermal path to the PC board makes the solution viable. The 5.3 x 6.2 x 0.8-mm package integrates a high-side power MOSFET with a drain-gate charge of 1.5 nC for a fast switching speed and high efficiency with a low-side power MOSFET that has a low on-resistance of 3.7 mΩ to reduce power loss and an integrated Schottky barrier diode. Multiple wirebonds at the high-side switch’s drain and the low-side switch’s source reduce the overall on-resistance of the half-bridge.
Talkback
DN's Resource Center Get Free Information, Made Easy
-
Friction, Wear and Lubrication Info from Society
Society of Tribologists and Lubrication Engineers | Design Guide
Request Item -
Best Practices for Green, Energy, and Supplier Challenges
Dell Computer Corp. | Web Event
Request Item
